1. Field of the Invention
The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device and method of manufacture which imposes tensile and compressive stresses in the device during device fabrication.
2. Background Description
Mechanical stresses within a semiconductor device substrate can modulate device performance. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs). However, the same stress component, either tensile stress or compressive stress, discriminatively affects the characteristics of an n-type device and a p-type device.
For example, it has been known that a device exhibits better performance characteristics when formed on a silicon layer (or cap) that is epitaxially grown on another epitaxially grown SiGe layer that has relaxed on top of the silicon substrate. In this system, the silicon cap experiences biaxial tensile strain. When epitaxially grown on silicon, an unrelaxed SiGe layer will have a lattice constant that conforms to that of the silicon substrate. Upon relaxation (through a high temperature process for example) the SiGe lattice constant approaches that of its intrinsic lattice constant which is larger than that of silicon. A fully relaxed SiGe layer has a lattice constant close to that of its intrinsic value. When the silicon layer is epitaxially grown thereon, the silicon layer conforms to the larger lattice constant of the relaxed SiGe layer and this applies physical biaxial stress (e.g., expansion) to the silicon layer being formed thereon. This physical stress applied to the silicon layer is beneficial to the devices (e.g., CMOS devices) formed thereon because the expanded silicon layer increases N type device performance and a higher Ge concentration in the SiGe layer improves P type device performances.
Relaxation in SiGe on silicon substrates occurs through the formation of misfit dislocations. For a perfectly relaxed substrate, one can envision a grid of misfit dislocations equally spaced that relieve the stress. The misfit dislocations facilitate the lattice constant in the SiGe layer to seek its intrinsic value by providing extra half-planes of silicon in the substrate. The mismatch strain across the SiGe/silicon interface is then accommodated and the SiGe lattice constant is allowed to get larger.
However, the problem with this conventional approach is that it requires a multi-layered SiGe buffer layer that is very thick (e.g., a thickness of approximately 5000 Å to 15000 Å) to achieve misfit dislocations on its surface portion while avoiding threading dislocations between the SiGe layer and the silicon substrate layer, thereby achieving a relaxed SiGe structure on the surface of the multi-layered SiGe layer. Also, this approach significantly increases manufacturing time and costs. Further, the thick graded SiGe buffer layer cannot be easily applicable to silicon-on-insulator substrate (SOI). This is because for silicon-on-insulator the silicon thickness has to be below 1500 Å for the benefits of SOI to be valid. The SiGe buffered layer structure is too thick.
Another problem is that misfit dislocations formed between the SiGe layer and the silicon epitaxial layer are random and highly non-uniform and cannot be easily controlled due to heterogeneous nucleation that cannot be easily controlled. Also, misfit dislocation densities are significantly different from one place to another. Thus, the physical stress derived from the non-uniform misfit dislocations are apt to be also highly non-uniform in the silicon epitaxial layer, and this non-uniform stress causes non-uniform benefits for performance with larger variability. Further at those locations where misfit density is high, the defects degrade device performances through shorting device terminals and through other significant leakage mechanisms.
It is also known to grow Si:C epitaxially on Si where it is inherently tensile. A 1% C content in a Si:C/Si material stack can cause tensile stress levels in the Si:C on the order of 500 MPa. In comparison, in the SiGe/Si system about 6% Ge is needed to causes a 500 MPa compression. This 1% level of C can be incorporated into Si during epitaxial growth as shown in Ernst et al., VLSI Symp., 2002, p 92. In Ernst et al., Si/Si:C/Si layered channels for nFETs are shown. However in the Ernst et al. structure, the Si:C is provided in the traditional strained Si approach as a stack of layers in the channel. Thus, in the Ernst et al. structure, the Si:C is used as part of the channel, itself. The problem with this approach is that the mobility is not enhanced, but retarded depending on the C content from scattering.